1. Field of the Invention
The present invention relates to circuitry for a programmable CMOS memory cell, the CMOS memory cell having PMOS and NMOS transistors with a common floating gate. More particularly, the present invention relates to such programmable CMOS memory cells which can be utilized in a programmable logic device (PLD).
2. Description of the Related Art
FIG. 1 illustrates a first type conventional CMOS memory cell having a PMOS transistor 102 and an NMOS transistor 104 with a common floating gate. The first type CMOS cell includes two capacitors 106 and 108 which are utilized to program and erase the common floating gate. Capacitor 106 supplies voltage from an array control gate (ACG) node. An NMOS pass transistor 110 supplies a word control (WC) voltage to capacitor 108 as controlled by a word line (WL) voltage supplied to its gate.
Further, in the first type cell of FIG. 1, drains of transistors 102 and 104 are connected together to form an output. Bias voltage is provided to the source of PMOS transistor 102 from a chip Vcc pin. Bias voltage is provided to the source of the NMOS transistor 104 through a chip ground or Vss pin. The CMOS memory cell of FIG. 1 is disclosed in U.S. Pat. No. 5,272,368 entitled "Complementary Low Power Non-Volatile Reconfigurable EECELL," and in U.S. Pat. No. 4,885,719 entitled "Improved Logic Cell Array Using CMOS E.sup.2 PROM Cells."
FIG. 2 shows a layout for the first type CMOS cell of FIG. 1 as formed in a p type substrate. In the layout, capacitor 106 includes an n+ type program junction implant region 202 formed in the p substrate. Separating the n+ type implant region 202 from the common floating gate (F.G.) 204 is an oxide layer approximately 150 .ANG. thick. Capacitor 108 includes an n+program junction implant region 206 formed in the p type substrate. Overlying the n+ type implant region 206 is the floating gate 204 which is separated from the implant region 206 by a gate oxide which includes a 150 .ANG.portion and a 85 .ANG. tunneling portion 208. The 85 .ANG. tunneling portion 208 enables charge to be applied to the floating gate 204 during program and removed during erase.
Further, in the CMOS cell of FIG. 1, transistor 110 is formed by a polysilicon (POLY) word line (WL) region on the substrate with a portion of the WL region adjacent the n+ implant region 206 and another portion adjacent an additional n+ implant region 210. Transistor 104 includes two n+ implant regions 212 and 214 in the p substrate. A gate oxide region of approximately 150 .ANG. separates a channel between regions 212 and 214 from the common floating gate 204. Transistor 102 includes two p type regions 216 and 218 in a n+ type well 220 which is included in the p type substrate. A gate oxide region of approximately 150 .ANG. separates the channel between regions 216 and 218 from the common floating gate 204.
Typical voltages applied for program, erase and read of the CMOS memory cell of FIG. 1 are listed in Table I below.
TABLE I ______________________________________ WC WL ACG Vcc Vss ______________________________________ Program Vpp Vpp+ 0 0 0 Erase 0 Vcc Vpp+ Vpp Vpp Read Vcc/2 Vcc Vcc/2 Vcc 0 ______________________________________
In Table I, as well as subsequent tables, programming indicates electrons are removed from the common floating gate, while erase indicates that electrons are added to the common floating gate. Further, Vpp indicates a programming voltage, typically of 12 volts. Vpp+ indicates the Vpp voltage plus an n channel threshold, typically totaling 13.8 volts. Finally, Vcc indicates a chip power supply pin voltage, typically of 5 volts.
FIG. 3 shows a second type CMOS memory cell design including a PMOS transistor 302 and an NMOS transistor 304 with a common floating gate. Unlike the capacitors 102 and 104 utilized in the first type CMOS memory cell of FIG. 1, the second type CMOS cell utilizes capacitor 306 and tunneling oxide regions in transistors 302 and 304 for program and erase. The capacitor 306 is connected between an array control gate (ACG) node and the common floating gate.
Further, in the CMOS cell of FIG. 3, the drains of transistors 302 and 304 are connected together to form the CMOS cell output. An additional PMOS pass gate transistor 310 has a drain connected to the source of PMOS transistor 302, a source connected to receive a word control (WC) voltage and a gate connected to receive a word line (WL) voltage.
FIG. 4 shows the layout for the cell of FIG. 3. As with the layout of FIG. 2, the capacitor 306 includes an n+ type program junction implant region 402 formed in the p type substrate. Separated from the n+ type implant region 402 by a 150 .ANG. thick gate oxide region is the common floating gate (F.G.) 406. The tunneling oxide windows 430 and 432 of approximately 85 .ANG. are provided between the floating gate 406 and the channel regions of respective transistors 302 and 304. The remaining regions of the common floating gate 406 are separated from the substrate by a 185 .ANG. oxide layer. The channel region of the NMOS transistor 304 is formed between its n+ source and drain implant regions 410 and 412. The channel region of the PMOS transistor 302 is formed in an n+ well between p+ implant regions 414 and 416. The PMOS pass transistor 310 is formed in the same n+ well as transistor 302, using the n+ implant region 416 as its source, an additional implant region 418 as its drain, and a polysilicon wordline (WL) forming its gate.
Voltages applied to the CMOS memory cell of FIG. 3 during program, erase and read are listed in Table II below.
TABLE II ______________________________________ WC WL ACG Vss ______________________________________ Program Vpp Vcc 0 Hiz Erase Hiz 0 Vpp 0 Read Vcc 0 Vcc/2 0 ______________________________________
With the second type CMOS memory cell programmed through the tunneling window of PMOS transistor 302, current leakage can occur to cause a disturb condition. Such a disturb condition occurs where electrons are injected onto the common floating gate in a CMOS cell which is not to be programmed. The current leakage during programming can occur because of charge storage in a large n well in which the PMOS transistors 302 and 310, as well as PMOS transistors of other CMOS cells are formed. A single n well is typically shared by a column of cells which all receive the same voltage WC during programming of a particular cell in the column. During programming a particular cell, a WL voltage of Vcc is applied, but in cells not to be programmed, a WL voltage of Vpp+is applied. The Vpp+WL voltage is applied to assure that the source of the PMOS transistors of unselected cells are floating, floating indicating a high impedance (Hiz) state. However, a large number of cells in an array will require a long Vss line, the long Vss line then having a significant capacitive component, enabling charge storage. By connecting the source of NMOS transistors of unselected cells in a column to the Vss line, a current flow can occur to charge up the capacitance of the Vss line so that drains of NMOS transistors and thus corresponding PMOS transistors are not floating. With the drain of an NMOS transistor not floating, electrons may be injected onto the floating gate in the unselected cells creating a disturb condition.
To avoid such a disturb condition, an additional NMOS transistor 500 can be added to the CMOS memory cell of FIG. 3, as shown in FIG. 5. Transistor 500 enables disconnection of the source of NMOS transistor 304 from the Vss line during programming to prevent a disturb condition. Such a CMOS memory cell is described in more detail in U.S. patent application Ser. No. 08/447,991, entitled "A Completely Complementary MOS Memory Cell With Tunneling Through The NMOS and PMOS Transistor During Program And Erase, filed May 23, 1995. Although the additional transistor 500 does help prevent a disturb condition, maintaining the drain of PMOS transistor 302 floating remains difficult, making a disturb condition likely.
FIG. 6 shows a programmable memory cell most commonly used in PLDs. The memory cell of FIG. 6 is manufactured similar to the first type cell of FIG. 1, with two capacitors 606 and 608 to control programming of a floating gate. The floating gate, however, is coupled only to a single transistor 604. As with the transistor 110 of FIG. 1, transistor 610 is utilized to apply voltages to capacitor 608. The gate voltage of transistor 610 is also applied to an additional NMOS transistor 602.
Because the cells of FIGS. 1 and 3 do not include a means to create a separate enable or disable, unlike the cells of FIGS. 5 and 6, their circuitry is not practical for use with a PLD. To illustrate, FIG. 7 shows the connections of two array cells 701 and 702 in a PLD. As shown, each array cell 701 and 702 receives an input signal COL1 and COL2 as an enable signal EN. Each of cells 701 and 702 further has one connection to a product term (PT) line and an additional connection to a product term ground (PTG) line. The PT line forms an input to a buffer 712 included in a sense amplifier 710. The PTG line provides a connection to Vss in the sense amplifier 710. The sense amplifier 710 also includes a current source 714 connected to the input of the buffer 312. Array cells 701 and 702 are programmed to provide a connection from the PT to the PTG line, the connection being provided when the array cell receives an appropriate EN signal.
By connecting the output of the cell of either FIGS. 1 or 3 to the PT line and its corresponding Vss connection to the PTG line, programming can provide a path between its output and Vss. However, no separate enable (EN) is provided. With the PT and PTG lines connected in FIG. 6 and the WL connection providing an enable, the cell of FIG. 6 is usable in a PLD. Similarly, with the output of the CMOS cell of FIG. 5 connected to the PT line, its Vss connection connected to the PTG line, and the gate of transistor 500 receiving the enable (EN) signal, the circuit of FIG. 5 can be used in a PLD. Unlike the cell of FIG. 6, a CMOS memory cell of FIG. 5 is advantageous because it enables zero power operation, zero power operation indicating that the component does not continually draw power when the component is not changing states.